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Chapter 4 - Assembler

The miSim DE Macro Assembler

miSim DE includes a fully featured Macro assembler that implements can support different processor mnemonics appropriate to the device being targetted. It is designed to be compatible with MPASM and similar assemblers.

The general syntax for each line of the assembly file is:

In general, each line will contain either a comment, a command for the assembler to follow, a machine instruction or will be blank. Labels are used to represent values to be used during assembly (for instance, a label might be used to represent the address of a subroutine). The assembler commands and machine instructions may take parameters, which can be labels, numbers or expressions.

Example lines for assembly:

Instruction Set

This is not meant as an introduction to the PIC® MCU family, as there are much better written texts on the subject. However, in version 2.0 the assembler will recognise the standard Microchip mnemonics for 12- and 14-bit microcontrollers. These are detailed below. The instructions shown with a grey background are only available for 14-bit devices.

InstructionMeaningStatus14-bit Opcode12-bit Opcode
NOP  No operation None 00 0000 0000 0000  0000 0000 0000  
CLRF f Clear f Z 00 0001 1fff ffff0000 011f ffff
CLRW  Clear W Z 00 0001 0000 00110000 0100 0000
MOVLW v Move Literal to W None 11 00xx vvvv vvvv1100 vvvv vvvv
MOVWF f Move W to f None 00 0000 1fff ffff0000 001f ffff
MOVF f,d   Move f Z 00 1000 dfff ffff0010 00df ffff
SWAPF f,d Swap halves f None 00 1110 dfff ffff0011 10df ffff
COMF f,d Complement f Z 00 1001 dfff ffff0010 01df ffff
Mathematic Instructions
ADDLW v Add literal to W C,DC,Z11 111x vvvv vvvv- n/a -
SUBLW v Subtract W from literalC,DC,Z11 110x vvvv vvvv- n/a -
ANDLW v AND literal and W Z 11 1001 vvvv vvvv1110 vvvv vvvv
IORLW v Incl. OR literal and W Z 11 1000 vvvv vvvv1101 vvvv vvvv
XORLW v Exclusive OR literal and WZ 11 1010 vvvv vvvv1111 vvvv vvvv
ADDWF f,d Add W and f C,DC,Z00 0111 dfff ffff0001 11df ffff
SUBWF f,d Subtract W from f C,DC,Z00 0010 dfff ffff0000 10df ffff
ANDWF f,d AND W and f Z 00 0101 dfff ffff0001 01df ffff
IORWF f,d Inclusive OR W and f Z 00 0100 dfff ffff0001 00df ffff
XORWF f,d Exclusive OR W and f Z 00 0110 dfff ffff0001 10df ffff
DECF f,d Decrement f Z 00 0011 dfff ffff0000 11df ffff
DECFSZf,d Decrement f, skip if zeroNone00 1011 dfff ffff0010 11df ffff
INCF f,d Increment f Z 00 1010 dfff ffff0010 10df ffff
INCFSZf,d Increment f, skip if zeroNone00 1111 dfff ffff0011 11df ffff
RLF f,d Rotate left f C 00 1101 dfff ffff0011 01df ffff
RRF f,d Rotate right f C 00 1100 dfff ffff0011 00df ffff
Control Instructions
CALL k Call subroutine at k None 10 0kkk kkkk kkkk1001 kkkk kkkk
GOTO k Goto address k None 10 1kkk kkkk kkkk101k kkkk kkkk
RETURN Return from subroutine None 00 0000 0000 1000- n/a -
RETFIE Return from Interrupt None 00 0000 0000 1001- n/a -
RETLW v Return with literal in WNone 11 01xx vvvv vvvv1000 vvvv vvvv
Bit Instructions
BCF f,b Bit clear f None 01 00bb bfff ffff0100 bbbf ffff
BSF f,b Bit set f None 01 01bb bfff ffff0101 bbbf ffff
BTFSC f,b Bit test, skip if clearNone 01 10bb bfff ffff0110 bbbf ffff
BTFSS f,b Bit test, skip if set None 01 11bb bfff ffff0111 bbbf ffff
Special Instructions
SLEEP  Processor Sleep TO,PD 00 0000 0110 00110000 0000 0011
CLRWDT Clear Watchdog timer TO,PD 00 0000 0110 01000000 0000 0100
OPTION Load OPTION register None - n/a -0000 0000 0010
TRIS f Tristate port f None 00 0000 0110 0fff0000 0000 0fff

Key:

In addition to these core instructions, the standard Microchip assembler supports a number of 'Alias' instructions which are short forms of those above. Some alias instructions encode to a specific single opcode. Others may encode to two separate processor instructions. The alias instructions are listed below:

InstructionParametersMeaningEquivalent
ADDCF f,dAdd Carry to RegisterBTFSC 3,0
INCF f,d
ADDDCFf,dAdd Digit Carry to RegisterBTFSC f,d
INCF 3,1
B kBranchGOTO k
BC kBranch on CarryBTFSC 3,0
GOTO k
BDC kBranch on Digit CarryBTFSC 3,1
GOTO k
BNC kBranch on No CarryBTFSS 3,0
GOTO k
BNDC kBranch on No Digit CarryBTFSS 3,1
GOTO k
BNZ kBranch on No ZeroBTFSS 3,2
GOTO k
BZ kBranch on ZeroBTFSC 3,2
GOTO k
CLRC  Clear CarryBCF 3,0
CLRDC  Clear Digit CarryBCF 3,1
CLRZ  Clear ZeroBCF 3,2
MOVFW fMove Register to WMOVF f,0
NEGF f,dNegate RegisterCOMF f,1
INCF f,d
SETC  Set CarryBSF 3,0
SETDC  Set Digit CarryBSF 3,1
SETZ  Set ZeroBSF 3,2
SKPC  Skip on CarryBTFSS 3,0
SKPDC  Skip on Digit CarryBTFSS 3,1
SKPNC  Skip on No CarryBTFSC 3,0
SKPNDC Skip on No Digit CarryBTFSC 3,1
SKPNZ  Skip on Non ZeroBTFSC 3,2
SKPZ  Skip on ZeroBTFSS 3,2
SUBCF f,dSubtract Carry from RegisterBTFSC 3,0
DECF f,d
SUBDCFf,dSubtract Digit Carry from RegisterBTFSC 3,1
DECF f,d
TSTF fTest RegisterMOVF f,1

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